The invention relates to the layout design and manufacture process of integrated circuits, and more particularly to a simulation methodology of defects interaction with layout design.
Defects may be randomly introduced during IC fabrication process. Some of these defects may cause electrical circuitry failures (open or short faults in general), and similar electrical failures are collectively referred to as certain failure mechanisms. For example, spot defects are caused by particles such as dust and other contaminants in materials and equipment. Open or short failures are considered from two types of mechanisms: “extra material” defects causing shorts between different conductive regions; and “missing material” defects causing open circuits. These defects may be randomly occurring particles of foreign matters, of varying sizes, during the manufacturing process. These defects can fatally cause an integrated circuit failure.
Conventionally, susceptibility of an integrated circuit to defects is estimated using complicated numerical methods, such as a computer-aided mathematical analysis of the integrated circuit mask layout. Typically, such an analysis requires complicated numerical methods and large amounts of computing and resources.
For example, the determination of the susceptibility of an integrated circuit to defects may be obtained by a computer analysis of the integrated circuit mask layout. It is common for such an analysis to require lots of computer time and a large amount of computer memory. A substantial cost must be incurred to estimate these properties and other properties of an integrated circuit.
A method commonly used to reduce the time to extract properties is to exploit the hierarchy of the integrated circuit design. In its simplest form the interactions between sub-cells, i.e., discrete areas of the design, are ignored. The technique consists of the analysis of each sub-cell within the design to estimate the property of the sub-cell. This property is then multiplied by the numbers of repeats of the sub-cell within the chip design. The technique is limited by the nature of the design hierarchy. Integrated circuits that are largely made up of multiple copies of a single or a few cells can be analyzed.
The simplified approach of hierarchical extraction of whole chip ignores interactions between cells. This might always lead to certain degree of inaccuracy. The level of inaccuracy is not easily predicted so that the results are less confident. In more complex embodiments interactions between cells are included. This ensures that the results are accurate, but at a cost. The implementation is considerable more difficult. The analysis takes longer since the interaction region, which can be large, must also be processed.